Silicon (Si) electronic devices have been around for as long as there have been electronics, but scaling-related issues have hampered their advancement [1]. Rapid development in complementary Metal–Oxide–Semiconductor (MOS) technology is based on making transistors smaller while keeping their functionality. With the reduced dimensions of field effect transistors based on Si, the dependableness and efficacy of these FETs are cause for concern. Also, their limitations in scaling and fabrication for leakage current and gate oxide thickness, the emergence effects of short channels in transistors, such as gate leakage current and subthreshold swing, further complicate the scaling process [2]. There have been numerous proposals for overcoming these limitations. Nanotubes are another fascinating structure that can further extend the scaling to build MOSFET [3]. One of the benefits of nanotubes for transistors is that they have high carrier mobility [4,5] since electrical transport in superior nanotubes may be ballistic [6,7]. A team of researchers from IBM has successfully fabricated a transistor composed of a 9-nm nanotube, demonstrating superior operational efficiency in comparison to other transistors of similar dimensions [8]. In addition to their organic counterparts, nanotubes of non-organic origin can also serve as a viable option for a transistor channel. Several types of nanotubes, such as Boron Nitride Nanotube (BN), Gallium Nitride (GaN), Silica and Nickel Halide, are readily accessible [9]. The focus of our study pertains to GaNNT and their application as channels in transistors. GaN has emerged as a very promising material due to its exceptional properties, making it suitable for numerous applications, such as high power, LED and high mobility applications. GaN exhibits a distinctive characteristic in the form of a stable hexagonal configuration [10]. GaN bulk transistors have demonstrated exceptional speed, enabling frequencies of up to 205 GHz, hence offering the potential to enhance the speed and cost-effectiveness of existing devices [11]. GaNNT has been observed to possess favorable electrical and optical characteristics, without any compromise on generality. The effective synthesis of single-crystal GaNNT has been achieved through the utilization of the epitaxial casting process [12]. Their uses as devices such as transistors are not well understood. To date, there has been a paucity of studies conducted on the subject matter of GaNNT transistors. In a similar vein to Carbon nanotubes, the utilization of GaNNT can be employed to generate field effect transistors. BN nanotubes have been identified as the precursor to GaNNT and they have been successfully synthesized and demonstrated semiconducting characteristics [13]. Despite belonging to same class as Nitride nanotubes of III-group, BN and GaN nanotubes exhibit different characteristics [14]. Through the utilization of Density Functional Theory (DFT) principles, simulation investigations have revealed that Boron Nitride and Carbon nanotubes exhibit analogous behaviors.

The primary objective of this investigation is to illustrate the benefits of utilizing GaN material in the design of MOSFETs through the implementation of simulation techniques as per the tenets of DFT. In addition, the study of their relative performance with gate lengths (L_g), dielectric constants and oxide thicknesses (t_ox) has been carried out in terms of improvement in short-channel effects. For the theoretical analysis of sub-5 nm DG GaNNT MOSFETs n- and p-type performance, we employed a quantum-transport ab initio methodology.

Computational Details

The simulation of transport properties is conducted using the DFT in conjunction with a nonequilibrium Green's function technique, as applied via the Atomistix ToolKit [15,16]. The drain current I_ds at a specific bias/gate voltage V_b/V_g is computed using Landauer-Büttiker formula [17]:

where, T(E, CN) V_b/V_g T(E, V_b, V_g) represents the transmission coefficient, whereas f_s(d) denotes the source (drain) Fermi-Dirac function. Additionally, m_s(d) indicates the Fermi potential for the source (drain). Specifically, the basis set that double ζ polarized is implemented. The exchange-correlation phenomenon is characterized by the utilization of a generalized gradient approximation inside the functional framework by Perdew Burke Ernzerhof with the adoption of the model of a single electron [18]. Since doping carriers largely mask the electron-electron interaction, the model of a single electron is qualified to describe an electronic device's structure [19,20]. The k-point grids [21] are defined using the Monkhorst-Pack scheme as 9×9×1 and 9×9×175 for the central region and the electrode region within the Brillouin zone, respectively. The mesh cutoff established at 125 hartrees, while the temperature maintained at 300 K. To avoid interlayer interaction, a vacuum space of 10Å is implemented as a boundary condition. The structure optimization process has been carried out until the energy difference per atom reaches 10^-6 eV. The boundary conditions are periodic in the x-direction, Neumann in the y-direction and Dirichlet in the z-direction, as illustrated in Figure 1. The direction of transportation is aligned with the z-axis.

Figure 1: Schematic View of DG GaNNT MOSFETs

The construction of the GaNNT MOSFET model involves the utilization of intrinsic GaNNT material L_g£5 mn as the channel. The design setup depicted in Figure 1 employs double gates, to utilize strongly n- or p-doped GaNNT as electrodes. The optimal doping concentrations for the electrodes are determined to be 4×10¹³ cm^-2 for n doping and 6×10¹³ cm^-2 for p doping, respectively, as per the results of the test. Gate lengths were set to range from 1to 5 nm, in 1nm steps with SiO₂, HfSiO₄, HfO₂, La₂O₃ and TiO₂ as the oxide dielectric material. The range for the oxide thickness is established to be between 0.1 and 0.5 nm, with increments of 1 nm and the supply voltage (V_dd = V_b = 0.5 V) is adopted for each device.

The I_on and I_off parameters are crucial metrics for evaluating the performance of logic transistors. A lower I_off value signifies lower static power dissipation, while a higher I_on value indicates enhanced operational speed of the device. The values of I_on in n-type MOSFETs are achieved by measuring the V_g (on) = V_g (off) + V_dd conversely, The I_on values for p-type MOSFETs are typically determined at the V_g (on) = V_g (off) - V_dd. Here, the V_g (off) for all devices is zero. Figure 2a and b illustrates the transfer features of the n-type and p-type DG GaNNT FETs with the L_g sub-5 nm for different gate lengths, oxide dielectric material and oxide thickness by adjusting the gate voltage within the range of 0 to 1 V at supply voltage V_dd = V_b (off) - V_dd = V_b = 0.5 V. The I_ds curves of n and p-type FETs at L_g = 5 nm with EOT = 0.1 nm show increased I_ds with higher gate dielectric materials, as represented in Figure 2c and d.

In these figures, the I_ds exhibits a greater magnitude when considering TiO₂ as compared to other dielectric materials. An increase in the dielectric constant leads to an increase in the gate capacitance, thereby resulting in an increase in the inversion charge. An elevation in the inversion charge leads to a corresponding augmentation in the I_ds due to the Low conduction band edge energy of FETs with a high dielectric material [22], implying that the process of conduction takes place at reduced energy levels, which makes the TiO₂ and the La₂O₃ materials are better candidates as gate dielectric. At L_g = 5 nm and SiO₂ dielectric layer, Figure 2e and f shows the decrease of driving current for the same gate voltage due to an increase in oxide thickness which leads to the reduction of gate capacitance [23].

Figure 2: Transfer Characteristics of DG GaNNT MOSFETs as a Function of (a, b) Gate Lengths, (c, d) Oxide Dielectric Material and (e, f) Oxide Thickness

The I_on/I_off ratio serves as a key metric for evaluating the performance of a device, as it reflects the ability to achieve high performance (large I_on value) while minimising leakage power (small I_off value). In this context, the value of I_on is determined when the V_g is equal to the threshold voltage (V_th), while the value of I_off is determined when V_g is set to 0 V. According to Figure 3a, it can be observed that there is an increase in the I_on/I_off ratio as the L_g is increased. The I_on/I_off ratio exhibits an increase as the L_g is extended, because the I_on experiences an increase while the I_off undergoes a drop. Moreover, it can be observed from Figure 3b that the I_on/I_off ratio exhibits an upward trend as the dielectric constant increases. In a similar vein, it can be observed from Figure 3c that there is a notable decrease in the I_on/I_off ratio as the t_ox is increased.

Figure 3: I_on/I_off Ratio of DG GaNNT MOSFETs as a Function of (a) Gate Lengths, (b) Oxide Dielectric Material and (c) Oxide Thickness

In order to assess the effectiveness of gate control, the SS holds significant importance [24]. Enhanced gate control is correlated with a reduced SS in subthreshold region. Based on the formula SS = ¶V_g/¶ log I_ds [25], the term SS represents the magnitude of the change in V_g required to induce a 1dec alteration in the current. According to the references [26,27] it is widely believed that long channel conventional MOSFETs, which typically have dimensions in the micrometer range, exhibit a fundamental SS limit of 60 mV/dec at ambient temperature. As depicted in Figure 4a, the SS values of the GaNNT MOSFETs exhibit a decreasing trend as the L_g increases. Notably, the SS value experiences a significant reduction from 95 to 78 mV/dec when L_g increases from 1 to 5 nm. The reduction of leakage from the source to the drain is achieved by raising the dielectric constant. This, in turn, effectively lowers the SS to 62 mV/dec when utilizing TiO₂ as the dielectric material, as depicted in Figure 4b. The value of SS exhibits a progressive increase as the t_ox increases, eventually reaching a value of 98 mV/dec at a thickness of 0.5nm, as depicted in Figure 4c.

Figure 4: Subthreshold Swing of DG GaNNT MOSFETs as a Function of (a) L_g (b) Oxide Dielectric Material and (c) t_ox

Transconductance an additional significant element, plays a role in regulating the behavior of the gate inside the sub-threshold region. This can be expressed as the derivative of drain current with respect to gate voltage, denoted as (g_m = ¶I_ds/¶V_g) [24]. A greater value of g_m is expected to enhance the capacity to control gates. Generally, the parameter g_m exhibits an upward trend as both L_g and the dielectric constant increase, as depicted in Figure 5a and b. Conversely, g_m experiences a decline when t_ox grows, as illustrated in Figure 5c.

Figure 5: Transconductance of DG SWAlNNT MOSFETs with L_g (a), Oxide Dielectric Material (b) and t_ox (c)

The characteristic of digital circuits is determined by their switching speed. The calculation of switching speed involves the utilization of the formula t = C_tV_dd/I_on [28]. In this equation, C_t represents the total capacitance, which is the combination of fringing capacitances (C_f) and channel capacitance (C_ch) [24]. The determination of C_ch can be accomplished by employing the formula C_ch = ¶ Q_ch/W¶ V_g, where Q_ch denotes the total Mulliken charge of the central region and W represents the channel width. Based on the reference provided [24], it is assumed that the value of C_f, the channel capacitance, is twice that of C_i, the intrinsic channel capacitance. In general, it can be observed from Figure 6a and b that the parameter t demonstrates a decreasing pattern with increasing values of L_g and the dielectric constant. In contrast, the variable T exhibits an upward trend as the parameter t_ox increases, as depicted in Figure 6c.

Figure 6: Delay Time of DG GaNNT MOSFETs with L_g (a), Oxide Dielectric Material (b) and t_ox (c)

In the context of MOSFET applications, the PDP, denoted as PDP = V_dd I_on t, serves as a significant metric for evaluating the switching energy for digital circuits. In Figure 7, an analysis was conducted on the Power-Delay Product (PDP) of 2D-channel GaNNT MOSFETs for both n-type and p-type. The results indicate that the PDP exhibits a little drop as the L_g and dielectric constant increase, as shown in Figure 7a and b. Whereas, it increases with the t_ox, as depicted in Figure 7c.

Figure 7: PDP of DG GaNNT MOSFETs with L_g (a), Oxide Dielectric Material (b) and t_ox s (c)

The performance of GaNNT MOSFETs, both n-type and p-type MOSFETs, has been examined using the ab-initio DFT technique. This investigation focused on the influence of gate length, oxide dielectric material and oxide thickness. The simulation findings demonstrate that the I_on/I_off ratio can be significantly enhanced by increasing the gate length and dielectric constant, as well as by decreasing the oxide thickness. For SS, the results indicate a notable enhancement in mitigating short channel effects as the gate length extended to 5 nm. In the context of t and PDP, it has been discovered that there is a notable enhancement in the short channel impact at the gate length increased, the dielectric constant is increased and the oxide thickness is decreased. This improvement is particularly prominent when considering a channel length of 5 nm for n-type devices. Therefore, GaNNT exhibits considerable promise as a channel material for the development of complementary MOSFETs suitable for both n-type and p-type devices.

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